EMI Problem Of Multilayer PCB Design

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For the proper functioning of integrated circuits (ICs), it is important to place the proper capacitance near the power pins of the IC. This helps in making the output voltage jump faster. However, this approach has some limitations. Due to the limited frequency response of the capacitor, the capacitor can't generate the harmonic power required to drive the IC output cleanly across the entire frequency band. Moreover, the transient voltage developed across the power rail creates a voltage drop across the decoupling inductor, which is the main source of common-mode electromagnetic interference (EMI).

To solve these problems, the power planes around the IC can be utilized as an excellent high-frequency capacitor that collects the energy leaked from discrete capacitors to provide high-frequency energy for clean outputs. Additionally, the power layer inductance is small, so the transient signal synthesized by the inductor is also small, thereby reducing the common mode EMI.

It is important to keep the connection of the power plane to the IC power pin as short as possible, as the rising edge of the digital signal is faster. It is preferable to connect it directly to the pad where the IC power pins are located.

To control common-mode EMI, the power plane must contribute to decoupling and have sufficiently low inductance. The power plane must be a well-designed power plane pair. The quality of the power plane depends on the delamination of the power supply, the materials of the layers, and the frequency of operation (i.e., the IC rise time). Normally, the power supply is separated by 6mils and the interlayer is FR4. The equivalent capacitance per square inch of the power plane is about 75pF. The smaller the interlayer spacing, the larger the capacitance.

Although there are not many devices with rising times of 100 to 300 ps, with the current rate of development, devices with rising times in the 100 to 300 ps range will occupy a high percentage. For circuits with a rise time of 100 to 300 ps, 3mil layer spacing will no longer apply for most applications. At that time, it is necessary to use a layering technique with a layer spacing of less than 1 mil and replace the FR4 dielectric with a material of high dielectric constant. Today, ceramic and pottery plastics meet the design requirements of 100 to 300 ps rise time circuits.

Although new materials and new methods may be introduced in the future, 3 to 6 mil spacing and FR4 dielectrics are common enough today for high 1-to-3 ns rise time circuits. They are enough to handle high-end harmonics and to make transient signals low enough. Therefore, common-mode EMI can be lowered to a large extent. The examples given in this paper for the design of a hierarchical stack of PCBs will assume a layer spacing of 3 to 6 mils.

EMI Problem Of Multilayer PCB Design

Electromagnetic shielding is crucial in electronic designs. To achieve this, a good strategy is to use layered stratified signal routing on one or several layers. These layers should be placed next to the power or ground plane. In terms of power supply, a good stratification strategy should be adjacent to the power plane and ground plane. The distance between the power plane and the ground plane should be minimized. This routing strategy is commonly referred to as "layering".

When it comes to PCB stack design, the following layering scheme can help shield and suppress EMI. This scheme assumes that the supply current flows on a single layer with single or multiple voltages distributed in different parts of the same layer. The multi-power layer situation will be discussed later.

There are several potential issues with the traditional 4-layer board design. Even if the signal layer is in the outer layer and the power source and the ground layer are in the inner layer, the distance between the power layer and the ground layer is still too large. If cost is a concern, there are two alternatives to traditional 4-layer boards that can improve EMI suppression. However, they are only suitable for applications where the onboard component density is low enough, and there is enough area around the component where the required power supply copper layer can be placed.

The first alternative is to use a layering scheme in which the outer layer of the PCB is the strata, and the middle two layers are the signal/power layer. The power supply on the signal layers is routed with a wide line to lower the path impedance of the supply current and the impedance of the signal microstrip path. From an EMI control perspective, this is the best 4-layer PCB structure available. The second alternative is to use the outer power source and ground and take the middle two floors signal. Although this alternative is an improvement over the traditional 4-layer board, the interlayer impedance is not as good as the traditional 4-layer board.

If trace impedance needs to be controlled, the layout of power and ground below the copper islands must be carefully routed. Also, the power supply or strata should be interconnected as much as possible between the copper islands to ensure DC and low-frequency connectivity.

If the component density is relatively large on a 4-layer board, it is advisable to use a 6-layer board instead. However, some laminate schemes in the 6-layer board design may not be good enough to shield the electromagnetic field and have little effect on reducing the transient signal of the power bus. This article discusses two examples.

In the first case, the power supply and ground are placed on the 2nd and 5th floors, respectively. This approach is quite correct from the viewpoint of signal impedance control, but due to the high copper resistance of the power supply, it is very unfavorable to control the common mode EMI radiation.

In the second example, power and ground are placed on the 3rd and 4th floors, respectively. This design solves the problem of copper-clad power. However, due to the poor electromagnetic shielding performance of the 1st and 6th floors, differential mode EMI increases. This design solves the problem of differential mode EMI if the number of signal lines on both outer layers is minimal and the trace length is short (less than 1/20 of the wavelength of the highest harmonics of the signal). Suppressing the differential mode EMI is particularly good when copper-free areas and copper-free areas are patched on the outer layer with no components and no trace areas (every 1/20 wavelength interval). It is necessary to connect the copper shop with the internal ground floor.

A general high-performance 6-layer board design usually has layer 1 and layer 6 as stratum, the first 3 and 4 go power and ground. EMI suppression is excellent due to the double-layer, double-layer signal line layer centered between the power plane and the ground plane. The disadvantage of this design is that the wiring layer has only two layers. If the outer traces are short and copper is removed in a trace-free area, the same stack can be achieved with a traditional 6-layer board.

Another 6-layer board layout for the signal, ground, signal, power, ground, signal, which can achieve the advanced signal integrity design environment. The signal layer is adjacent to the ground plane, and the power plane and ground plane are repaired. The downside is that the layers of the stack are unbalanced. This usually causes problems for manufacturing. The solution to this problem is to fill all the blank areas of the third layer with copper, connecting the copper area to power or ground. The distance between the connecting vias is still 1/20 of the wavelength, not necessarily everywhere, but ideally should be connected.

Due to the very thin insulating isolation between the layers of a multilayer board, the impedance between the 10 or 12-layer board layers is very low, and excellent signal integrity is perfectly expected as long as there is no problem with delamination and stacking. 12-layer board manufacturing is more difficult than 10-layer board manufacturing since there aren't many manufacturers who can process boards that thin.

For the 10-layer board design, the signal layer and the circuit layer must be adjacent to each other. The board layout should be signal, ground, signal, signal, power, ground, signal, signal, ground, and signal. This design provides a good path for the signal current and its return current. The proper routing strategy is that the first layer is routed in the X direction, the third layer is routed in the Y direction, the fourth layer is routed in the Z direction, and so on. Layers 1 and 3 are a pair of tiered layers, Layers 4 and 7 are a pair of tiered layers, and Layers 8 and 10 are the last pair of tiered layers. When you need to change the direction of alignment, the signal line on layer 1 should be "vias" to layer 3 and then change direction. Similarly, when the alignment of the signal changes, it should be through the vias from the 8th floor and the 10th floor or from the 4th floor to the 7th floor. This routing ensures that the coupling between the signal's forward path and the loop is the tightest.

Conclusion

It's important to note that this article's discussion on board delamination and stacking is limited to circuit boards that are designed to be 62mil thick, with no traditional pubs with blind holes or buried holes. If the thickness difference between circuit boards is too great, or if the board includes blind hole or buried circuit board processing, the method of stratification recommended in this article may not be ideal.

The key to solving circuit board issues is not solely dependent on thickness, through-hole process, and the number of layers. Rather, excellent stratification is crucial to ensure proper power bus bypass and decoupling, as well as to minimize transient voltage on the power or ground layer, and to provide proper electromagnetic shielding for both signal and power. Ideally, there should be an insulating barrier between the signal routing layer and its return path ground plane, and the paired layer spacing (or more than one pair) should be as small as possible. By following these basic concepts and principles, we can design circuit boards that always meet design requirements.

As integrated circuit (IC) rise times become shorter, the techniques discussed in this article become increasingly necessary to solve electromagnetic interference (EMI) shielding issues.

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